1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an internal voltage generating circuit.
2. Description of Related Art
In some cases, a semiconductor integrated circuit device uses a plurality of internal voltages different from an external power supply voltage (hereinafter referred to as VCC) for ensuring the reliability, reducing power consumptions, ensuring operations, and so on. These internal voltages include a variety of types, such as a positive internal voltage lower than VCC, a positive internal voltage higher than VCC and a negative internal voltage lower than an external ground voltage (hereinafter referred to as GND). These internal voltages are generated by their corresponding internal voltage generating circuits, and driven into a predetermined voltage with the charge of parasitic and stabled capacitances formed within a semiconductor substrate. Furthermore, it is necessary to complete a setup operation at the time of setup such as power-on of the semiconductor integrated circuit device so that these internal voltages reach a predetermined electric potential within a time period defined by specifications.
For the semiconductor integrated circuit device, for example a DRAM which is one type of semiconductor storage device, a memory cell comprises one cell transistor and one cell capacitor. An internal voltage VBB for a back gate bias (hereinafter referred to as VBB), which is a negative voltage, is applied to a back gate region of the cell transistor. An internal voltage VPLT for a cell plate (hereinafter referred to as VPLT) is applied to an opposite electrode of the cell capacitor. Furthermore, an internal voltage VBL for precharge of a bit line pair (hereinafter referred to as VBL), an internal voltage VPP for setting of a word line (hereinafter referred to as VPP), which is higher in electric potential than VCC, as a selection voltage for a word line, and an internal voltage VNN for reset of a word line (hereinafter referred to as VNN), which is at a negative electric potential, as a non-selection voltage for a word line are used.
Internal voltages used in a memory core region on which memory cells are formed, for example VBB, VPLT, VBL, VPP, VNN are driven into a predetermined voltage by charging a parasitic capacitance between impurity diffusion regions within the memory core region. Furthermore, these internal voltages are mutually capacitive-coupled through the parasitic capacitance.
In order to generate a positive internal voltage higher than VCC and a negative internal voltage lower than GND as described above, the internal voltage is generally driven into a predetermined electric potential using a charge pump circuit comprising a capacitive element. There are various kinds of factors that determine the current drive capacity of the charge pump, but one of the major factors is the area of the capacitive element. The current drive capacity of the charge pump circuit is proportional to the area of the capacitive element. Therefore, for increasing the current drive capacity of the charge pump circuit, the area of the capacitive element included in the charge pump circuit may be increased. However, high integration is hindered because the block area of the charge pump circuit increases. Thus, it is necessary to make a design to decrease the current drive capacity of the charge pump circuit so that the circuit area becomes as small as possible while ensuring a necessary and sufficient capacity in consideration of loads on the charge pump circuit at the time of power-on setup operation, standby operation and active operation.
Incidentally, as the process has become precise and the capacity of memories has been increased in recent years, a parasitic capacitance to be charged within a memory core has increased, and accordingly, it has become necessary to increase the current drive capacity of the internal voltage generating circuit. For example, VBB is generated only by biasing the back gate region of the cell transistor to a negative voltage at the time of standby operation and active operation, and the VBB generating circuit may have a moderate current drive capacity capable of absorbing voltage variations by a leak current. However, at the time of power-on setup operation, a parasitic capacitance to be charged increases, and therefore a high current drive capacity corresponding to the parasitic capacitance is required.
When a design is made to increase the current drive capacity of the VBB generating circuit in accordance with the power-on setup operation, it is necessary to increase the capacitive element of the charge pump circuit, and the area of the circuit becomes so large that high integration is hindered. Conversely, when a design is made to decrease the current drive capacity of the VBB generating circuit in accordance with the standby operation, it may be impossible to complete the power-on setup operation so that a predetermined electric potential is reached within a time period defined by specifications. In this connection, explanations are presented here for VBB, but the same applies for internal voltages other than VBB.
Thus, a semiconductor integrated circuit device is known which drives (overdrive) VPLT and the like to be higher than an originally required electric potential at the time of power-on setup and then reduces, by a coupling capacitance, VBB connected to VPLT by the coupling capacitance at the time of drop in voltage after the overdrive (see, for example, Patent Documents 1 and 2). According to such a semiconductor integrated circuit device, a capacity of driving the internal voltage into a negative voltage at the time of power-on setup operation can be reinforced without increasing the drive capacity of the internal voltage generating circuit for VBB. Therefore, the drive capacity at the time of power-on setup can be reinforced without increasing the circuit scale of the VBB generating circuit itself, thus allowing the power-on setup of VBB in a short time.
[Patent Document 1] Japanese Patent Laid-Open No. 2004-334583 (FIG. 2)
[Patent Document 2] Japanese Patent Laid-Open No. 2005-353186 (FIGS. 4 and 15)
Incidentally, when a negative internal voltage and another negative internal voltage are mutually coupled by a parasitic capacitance, e.g. VBB and VNN are mutually coupled by a parasitic capacitance, Patent Document 2 discloses two types of methods for driving these internal voltages. FIG. 5 is a time chart showing a change in voltage waveform of each part of a semiconductor integrated circuit device according to a first method (corresponding to FIG. 15 of Patent Document 2). In FIG. 5, VPLT, VBB and VNN are fixed to GND until time T1. At time T1, VPLT is increased toward an electric potential V4 higher than a normal predetermined electric potential V5 (overdrive operation).
When VPLT reaches the electric potential V4 at time T2, the overdrive operation is stopped. In the overdrive operation at time T1 to T2, VBB and VNN are fixed to GND (clamp state).
At time T2 when VPLT reaches the electric potential V4, the clamp of VBB and VNN to GND is cancelled to reduce VPLT to the normal predetermined electric potential V5 (voltage drop state). VBB decreases from GND toward a negative voltage by capacitive coupling, since it is coupled through the coupling capacitance of VPLT and VBB. After time T2, VBB ultimately reaches a predetermined negative electric potential V7 due to depressing by the drive capacity of the VBB generating circuit itself and the coupling capacitance with VPLT (at time T3). After time T3, VBB is driven so as to be kept at the predetermined negative electric potential V7.
Furthermore, at time T2, a coupling capacitance exists between VNN and VBB, and therefore following a reduction in VBB, the electric potential of VNN decreases by capacitive coupling. VNN operates so that it reaches the negative electric potential V7 as in the case of VBB at time T3, and the electric potential of VNN after time T3 is kept at the negative electric potential V7 as in the case of VBB.
According to the first method, if it is desired to make VNN and VBB different, it is necessary to increase an output drive capacity in a VNN generating circuit for canceling charges supplied by the coupling capacitance to drive the voltages into further desired voltages. Thus, it is necessary to increase a circuit scale related to the VNN generating circuit.
FIG. 6 is a time chart showing a change in voltage waveform of each part of a semiconductor integrated circuit device according to a second method (corresponding to FIG. 4 of Patent Document 2). In FIG. 6, the explanations of the process until time T2 are omitted because it is same as that in FIG. 5. At time T2 when VPLT reaches the electric potential V4, the clamp of VBB to GND is cancelled to reduce VPLT to the normal predetermined electric potential V5 (voltage drop state). VBB decreases from GND toward a negative voltage by capacitive coupling, since it is coupled through the coupling capacitance of VPLT and VBB. After time T2, the electric potential of VBB ultimately reaches the predetermined negative electric potential V7 due to depressing by the drive capacity of the VBB generating circuit itself and the coupling capacitance with VPLT (at time T3). After time T3, VBB is driven so as to be kept at the predetermined negative electric potential V7.
Furthermore, VNN is clamped to GND until time T3, and the clamp of VNN to CND is cancelled at time T3. After time T3, VNN ultimately reaches a predetermined negative electric potential V6 due to the drive capacity of the VNN generating circuit itself (at time T4). After time T4, VNN is driven so as to be kept at the predetermined negative electric potential V6.
According to the second method, there is the concern that time for completion of the setup is prolonged to time T4, thus making it difficult for VNN to reach a predetermined negative electric potential within a time period defined by specifications.
As described above, in the related art, there is the concern that an output voltage cannot be set to a desired voltage within a predetermined time period without increasing the circuit scale of the voltage generating circuit. In this connection, explanations have been presented for VBB and VNN in the above description, but the same applies for combinations of internal voltages other than VBB and VNN.